Architecture of A2DDC receiver:

Basic specifications:

Full-scale Input level: Single-ended 1.2 Vpp into 50 Ohm (+5.5 dBm) or Differential 2x 0.6 Vpp into 50 Ohm (2x -0.5 dBm)
Analog bandwidth: 0.3 MHz to 130 MHz (- 3 dB)
Sample clock frequency: up to 65 MHz
Digital channels: 2
Decimation: 2 to 16384
Max. pass band: 1.3 MHz (FIR 50 taps, fs 65 MHz)
Max. data size: 1M x 16 bit (2 ws)
Audio output: stereo sigma-delta DAC 16 bit
Power Supply: 5 V, typ. 4W

Basic measurements:

Dynamic range at fin 2.2 MHz : 149 dBFS/sqrt(Hz) @ fs 66 MHz
Dynamic range at fin 211 MHz : 143 dBFS/sqrt(Hz) @ fs 66 MHz
System jitter: <0.3 ps @ on-board 66 MHz clock
Intermodulation distortion: not measured yet
SFDR: not measured yet

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Pictures of some measurements: